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DTSTART;VALUE=DATE:20260423
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DTSTAMP:20260508T061603
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UID:400-1776902400-1777075199@www.wssp.hlrs.de
SUMMARY:41st Workshop on Sustained Simulation Performance
DESCRIPTION:Agenda\nAll times are given in Central European Summer Time (CEST).  \n\n\n\n\n\nThursday\, April 23rd\, 2026\n\n\n\n\n09:00\nRegistration Desk Opens\n\n\n09:45 – 10:00\nWelcome & Introduction\nMichael Resch\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n10:00 – 10:30\nA brief case study of “AI for Science” at the Cyberscience Center\nHiroyuki Takizawa\,Cyberscience Center\, Tohoku University\n\n\n\n10:30 – 11:00\nHLRS – Status and Outlook\nMichael Resch\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n\n11:00 – 11:30\nCoffee Break\n\n\n11:30 – 12:00\nOne Year of HUNTER from a User Perspective: Progress\, Performance\, and Patience with NS3D\nChristoph Wenzel\, Institute of Aerodynamics and Gas Dynamics\, University of Stuttgart\n\n\n\n12:00 – 12:30\nD3 Center’s strategy and project for supporting academic research in the “AI for Science” era\nSusumu Date\, The University of Osaka\n\n\n\n12:30 – 13:30\nLunch Break\n\n\n13:30 – 14:00\nImpact of GPU Virtualization on LLM Inference Performance: A Comparative Study of Bare Metal\, vGPU\nQifeng Pan\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n\n14:00 – 14:30\nThoughts on current and future HPC&AI installations\nSabine Roller\, Institute of Software Methods for Product Virtualization\, German Aerospace Center (DLR e.V.)\n\n\n\n14:30 – 15:00\nAeroacoustic Optimization of a Chevron Nozzle on the Hunter HPC System\nMatthias Meinke\, Institute of Aerodynamics\, RWTH Aachen University\n\n\n\n15:00 – 15:30\nCoffee Break\n\n\n15:30 – 16:00\nEvaluating a Real-Time Lossy Array Compression Algorithm for a Lattice Boltzmann Solver\nDarjan Krijan\, High-Performance Computing Center Stuttgart\, University of Stuttgart\nComputer simulations that were previously regarded as CPU-bound become gradually memory-bound as the growth in memory bandwidth cannot keep up with the much higher advancements in raw computing power. This imbalance is quantified with a relative factor of approximately 5.1 per decade since the 1990s\, where a rise in memory bandwidth is met with a 5.1-times increase in relative computing power. In practical terms\, comparing a NEC SX-4 from 1994 that operated at a balanced arithmetic intensity of 0.125 FLOP/Byte with an Intel Ponte Vecchio accelerator from 2023 that operates at 15.9 FLOP/Byte shows a factor of 127 in the described imbalance. Mixed-precision approaches that were traditionally used to speed up the throughput of calculations on a CPU core level now provide speedup due to less demanded memory bandwidth. Approaches to compress arrays in a lossless or lossy manner to reduce memory bandwidth were implemented in LLNL’s zfp library\, although it is not able to process the data in real-time. In this work\, a similar approach targeting a real-time lossy array compression (RTLAC) algorithm utilizing known value ranges of variables was developed and applied to a Lattice Boltzmann method for CFD simulations. Here\, the main simulation variables are within certain bounds\, making them ideal candidates for the RTLAC approach. Accuracy and performance results of the algorithm implemented in the m-AIA solver framework with multiple compression sizes will be presented.\n\n\n\n16:00 – 16:30\nFlowSimulator: A framework for multidisciplinary simulations for virtual aircraft\nJulian Braun\, Institute of Software Methods for Product Virtualization\, German Aerospace Center (DLR e.V.)\nMultidisciplinary simulations are essential for modern aerospace engineering. Applications include static aeroelastic coupling\, flutter analysis\, time-resolved aeroelastic simulations\, and gradient-based shape optimization. Highly specialized codes are able to compute high-fidelity solutions in their respective domain\, but external frameworks are needed to establish the coupling between them. This talk presents FlowSimulator and its approach for flexible and performant in-memory coupling. FlowSimulator is an environment which contains a variety of independent codes such as CFD for ONERA\, DLR and Airbus (CODA) and the structure solver b2000++pro. It follows a layered approach: users orchestrate their own workflows in Python\, while data exchange between simulation codes is realized on a C++ layer through MPI-parallel data structures for grids and simulation data. This allows for rapid prototyping as well as for performant\, parallel data exchange. Following a discussion of the design\, an outlook on fluid–structure interaction between high-order codes will be provided.\n\n\n\n16:30 – 17:00\nMPPI – Type safe C++ Datatypes for MPI\nMike Söhner\, High-Performance Computing Center Stuttgart\, University of Stuttgart\nMPI provides a flexible C-API to communicate data of various types between a set of distributed processes over high-speed interconnects in HPC systems. Data buffers are described using MPI-Datatypes\, which specify the type and layout of the data to be transmitted. To construct these datatypes\, users must manually describe the memory layout of buffer elements via the MPI-API. However\, modern applications are typically written in object-oriented C++\, which offers significant advantages over C\, including type safety and metaprogramming capabilities.\nIn this work\, we introduce a new C++-API and datatype engine that leverage C++ language features such as concepts\, ranges\, and the upcoming reflection to extract the necessary datatype information for the user at compile-time. This approach simplifies the user’s work\, enhances code safety by eliminating manual datatype construction and offers previously unavailable possibilities. Our measurements demonstrate that this interface introduces no performance overhead and\, in some cases\, even improves performance.\n\n\n\n\n\nFriday\, April 24th\, 2026\n\n\n\n\n09:00\nRegistration Desk Opens\n\n\n09:30 – 10:00\nToward Anomaly Prediction in HPC Systems\nRyusuke Egawa\, School of Engineering\, Tokyo Denki University\n\n\n\n10:00 – 10:30\nRISC-V Vector Architecture & Programming Model\nFredrik Unger\, Openchip & Software Technologies\nIntroduction to RISC-V Vector architecture and programming model. A view on how the vector architecture differentiates from traditional scalar processors and GPU-based accelerators\, what the RISC-V open ISA with vector extensions brings to the HPC ecosystem\, and basic differences with respect to the programming model.\n\n\n\n10:30 – 11:00\nCoffee Break\n\n\n11:00 – 11:30\nFuture Computing: Researching and Working with the Cerebras Wafer Scale Engine\nJonathan Schäfer\, High-Performance Computing Center Stuttgart\, University of Stuttgart\nWe present general remarks on researching and working with the Cerebras Wafer-Scale Engine (WSE). We discuss the programming model\, current efforts worldwide and in our group to implement non-AI workloads on the WSE\, and some preliminary and submitted results.\n\n\n\n11:30 – 12:00\nPatient-Specific Hemodynamic Simulations with SPH: Challenges and Implementation Pipeline\nNiklas Neher\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n\n12:00 – 12:30\nTowards Energy‑Aware HPC: Measuring Efficiency Across Heterogeneous Hardware with HWS\nDirk Pflüger\, Scientific Computing – Institute of Parallel and Distributed Systems\, University of Stuttgart\nEnergy efficiency has become a critical aspect of sustained high‑performance computing. Yet for developers\, obtaining reliable energy metrics remains challenging due to mixed hardware environments\, varying vendor interfaces\, and limited portability of measurement tools. In this talk\, we present HWS\, our HardWare Sampling library that offers uniform\, low‑overhead access to performance and power data acrossCPUs and GPUs. HWS enables detailed energy efficiency analysis in heterogeneous HPC systems. We further show comparative results from benchmark applications implemented in SYCL\, illustrating how the combination of HWS and SYCL supports energy‑aware optimizations and fair cross‑architecture performance evaluations.\n\n\n\n12:30 – 13:30\nLunch Break\n\n\n13:30 – 14:00\nEnhancing Research with Provenance Management for HPC and AI Systems\nYosuke Taira\, NEC Corporation\n\n\n\n14:00 – 14:30\nTools for Rapid and Efficient I/O for Exascale\nPatrick Vogler\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n\n14:30\nFarewell\nMichael Resch\, High-Performance Computing Center Stuttgart\, University of Stuttgart\n\n\n\n 
URL:https://www.wssp.hlrs.de/events/41st-workshop-on-sustained-simulation-performance/
LOCATION:HLRS\, Nobelstraße 19\, Stuttgart\, Baden-Württemberg\, 70569\, Germany
ORGANIZER;CN="Mr. Benjamin Schnabel":MAILTO:schnabel@hlrs.de
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